# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            bswap_s32
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: bswap_s32
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
    ; CHECK: $w0 = COPY [[REVWr]]
    %0(s32) = COPY $w0
    %1(s32) = G_BSWAP %0
    $w0 = COPY %1
...

---
name:            bswap_s64
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: bswap_s64
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
    ; CHECK: $x0 = COPY [[REVXr]]
    %0(s64) = COPY $x0
    %1(s64) = G_BSWAP %0
    $x0 = COPY %1

...
---
name:            bswap_v4s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: bswap_v4s32
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[REV32v16i8_:%[0-9]+]]:fpr128 = REV32v16i8 [[COPY]]
    ; CHECK: $q0 = COPY [[REV32v16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<4 x s32>) = COPY $q0
    %1:fpr(<4 x s32>) = G_BSWAP %0
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            bswap_v2s32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: bswap_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[REV32v8i8_:%[0-9]+]]:fpr64 = REV32v8i8 [[COPY]]
    ; CHECK: $d0 = COPY [[REV32v8i8_]]
    ; CHECK: RET_ReallyLR implicit $d0
    %0:fpr(<2 x s32>) = COPY $d0
    %1:fpr(<2 x s32>) = G_BSWAP %0
    $d0 = COPY %1(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            bswap_v2s64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: bswap_v2s64
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK: [[REV64v16i8_:%[0-9]+]]:fpr128 = REV64v16i8 [[COPY]]
    ; CHECK: $q0 = COPY [[REV64v16i8_]]
    ; CHECK: RET_ReallyLR implicit $q0
    %0:fpr(<2 x s64>) = COPY $q0
    %1:fpr(<2 x s64>) = G_BSWAP %0
    $q0 = COPY %1(<2 x s64>)
    RET_ReallyLR implicit $q0

...
